The continual demand for enhanced integrated circuit performance has resulted in, among other things, a dramatic reduction of semiconductor device geometries, and continual efforts to optimize the performance of every substructure within any semiconductor device. A number of improvements and innovations in fabrication processes, material composition, and layout of the active circuit levels of a semiconductor device have resulted in very high-density circuit designs. Increasingly dense circuit design has not only improved a number of performance characteristics, it has also increased the importance of, and attention to, semiconductor material properties and behaviors.
The increased packing density of the integrated circuit generates numerous challenges to the semiconductor manufacturing process. Nearly every device must be smaller without degrading operational performance of the integrated circuitry. High packing density, low heat generation, and low power consumption, with good reliability must be maintained without any functional degradation. Increased packing density of integrated circuits is usually accompanied by smaller feature size and, correspondingly, smaller device geometries.
As semiconductor feature sizes and geometries are reduced, certain device structures become more sensitive to physical properties and behaviors of other nearby device structures. Minor changes in placement or configuration of a device structure can have a significant impact on the lifetime performance or reliability of an integrated circuit. Balancing competing sensitivities and characteristics of different structures within a circuit can be further complicated by technology-imposed design or layout limitations. A number of high-performance device fabrication technologies must impose certain design constraints (e.g., maximum interconnect width, maximum oxide thickness, minimum gate length) in order to provide required performance levels (e.g., low voltage operation).
Consider, for example, certain issues that arise during the production of certain CMOS transistor devices. Certain manufacturing processes often cause, directly or indirectly, disproportionately high stresses on critical CMOS features and structures. One CMOS device feature of particular concern is gate oxide. The electrical integrity and stability of gate oxide structure is critical to overall transistor performance and reliability. However, CMOS transistor gate oxides are extremely vulnerable to structural and parametric breakdown caused by electrical stresses generated within a semiconductor structure. This is especially true of relatively shallow gate oxides that are increasingly common in high performance commercial technologies. Generally, such gate oxides are substantially shallower than other surrounding oxide structures (e.g., field oxides), and therefore tend to be much more vulnerable. Partial or complete break down of, or damage to, such oxide structures can drastically degrade device performance, or destroy a device completely—having a significant detrimental impact on process yield or device reliability or performance.
A number of electric stresses—that may cause or contribute to the break down of gate oxide structures—occur during actual operation or testing of a post-fabrication semiconductor device. There are a number of electrical stresses, however, that occur during the fabrication of a semiconductor device that may potentially be as or more damaging than the post-fabrication stresses. Some such stresses are recognized and understood, and may be addressed in conventional fabrication processes. Other fabrication-related stresses may have not yet been recognized, or may have been recognized but not fully understood or addressed.
One apparently heretofore unrecognized or unaddressed phenomenon involves gate oxide damage induced by antenna-like capacitive coupling charges, and the effects of their discharge, emanating from collateral structures. This is particularly problematic when device structures in contact with or in proximity to a gate oxide structure are formed in certain conductor/insulator/conductor patterns—such as in the formation of capacitors within a semiconductor device.
A number of semiconductor processes (e.g., deposition, implant, plasma etch) are capable of inducing a charge on semiconductor structures formed of certain conductive materials (e.g., polysilicon, metal). In some cases, charge induced by semiconductor processes on a first conductive layer or structure may or may not be sufficient to overstress or fully break down an adjacent gate oxide structure directly or indirectly coupled thereto. Where, however, additional charge—induced by semiconductor processes on a second conductive layer or structure—capacitively couples with the charge already existing in the first conductive structure, overstress or fall breakdown of the adjacent gate oxide often results. In many cases, the accumulated charge discharges to the substrate through the least resistive path (i.e., the gate oxide structure). This phenomenon is particularly problematic where the first and second conductive structures are disposed or configured in a capacitor or quasi-capacitor arrangement, having an insulating layer or structure disposed therebetween. Charge build-up and discharge is, in many cases, an inherent or intended operational characteristic of such arrangements. Unfortunately, although such structures and configurations are common and necessary in semiconductor device design and fabrication, their charge and discharge during device fabrication are often not recognized or accounted for.
As a result, there is a need for a system that effectively dissipates charge accumulated within semiconductor device structures—particularly capacitors and capacitor-like arrangements—during fabrication that limits damage to surrounding structures caused by the dissipation or discharge of that charge, improving overall circuit and system performance and reliability in an easy, efficient and cost-effective manner.